PACT 2017

International Conference on 
Parallel Architecture and Compilation Techniques
PACT-2017
Portland, Oregon, USA
Sep 9-13, 2017


Dates & Deadlines:

  • March 14, 2017: Paper Deadline
  • May 3-6, 2017: Author Response Period
  • May 24, 2017: Author Notification
  • July 19, 2017: Camera Ready Final Papers
  • September 9-13, 2017: PACT 2017


PACT 2017 Information:

Call for Contributions

Program

Registration

Location


PACT 2017 Organization:


Previous PACTs:
PACT16 PACT15 PACT14 PACT13 PACT12 PACT11 PACT10 PACT09 PACT08 PACT07 PACT06 PACT05 PACT04 PACT03 PACT02 PACT01 PACT00 PACT99

Technical Sponsors




Address questions to: mi.sun.park [at] intel.com

The 26th International Conference on
Parallel Architectures and Compilation Techniques (PACT)
Portland, Oregon, USA
September 9-13, 2017


Intel® AVX-512 Architecture Insights, Compiler Optimizations and Code Modernization

Xinmin Tian, Bret Toll and Vladimir Polin (Intel Corporation)


Abstract:
The capabilities and performance potential of the SIMD HW technology have grown significantly in recent years. An increasing number of developers are finding SIMD to be a compelling technology and the adoption of vector programming is growing. Intel® Xeon® Scalable processors provide a rich set of SIMD instruction (gather/scatter, shuffles, FMA, permutations, etc.) and wider vector registers. With the emerging Intel® AVX-512, the biggest extension to Intel Instruction Set Architecture (ISA), the next generation of Intel’s multicore and many-core product lines will be built around its features such as wider SIMD ALU, more vector registers, new masking architecture for predication, embedded broadcast and rounding capabilities and the new integer/floating-point instructions. AVX-512 ushers in a new era of converged ISA computing in which the application developer needs to utilize these hardware features through programming tools for highly optimal performance.

This tutorial brings the Intel® AVX-512 ISA insights to the Parallel Architecture and Compilation Technology Community. The first part covers AVX-512 architecture, design philosophy, key features and its performance characteristics. The second part covers the programming tools such as compilers and the profilers that support the new ISA in a parallel programming framework to guide the developers step-by-step to turn their scalar serial applications into parallel and vector applications. Central to the second part is the explicit vector programming methodology under the new industry standard, OpenMP* 4.5. In the third part, we will present many real usage examples that illustrate how the power of the compiler can be harnessed with minimal user effort to enable SIMD parallelism with AVX-512 instructions from high-level language constructs.


Schedule:

  • 08:00 - 08:30: Checkin and Introduction
  • 08:30 - 09:30: Intel® AVX-512: Architecture Insights
  • 09:30 - 10:00: Compiler Tuning for Intel® AVX-512 (I)
  • 10:00 - 10:30: Coffee Break
  • 10:30 - 11:00: Compiler Tuning for Intel® AVX-512 (II)
  • 11:00 - 12:00: Code Modernization: Best Practices for Intel® AVX-512
  • 12:00 - 13:00: Lunch