https://parasol.tamu.edu/pact17/images/cisc_image.png

Organizing Chairs:

Ramesh Illikkal              Intel                      ramesh.g.illikkal@intel.com

Omesh Tickoo                Intel Labs             omesh.tickoo@intel.com

Hadi Esmaeilzadeh        GeorgiaTech         hadi@cc.gatech.edu

 

 

 

 

 

CISC 2017 - Preliminary Program

 

8:30 AM

 

Welcome & Workshop Introduction

8:30 AM

9:10 AM

 

Keynote - Towards Approximate and Probabilistic Computing: Opportunities and Challenges

Dr. Ravi Iyer

Intel Fellow,
Data Center Group, Intel Corporation

9:10 AM

9:35 AM

 

Accelerator Templates and Runtime Support for variable precision CNN

Srivatsan Krishnan, Piotr Ratusziak, Chris Johnson, Duncan Moss*, and Suchit Subhaschandra

Intel Corporation
*University of Sydney

9:35 AM

10:00 AM

 

Enabling Extreme Energy Efficiency Via Timing Speculation for Deep Neural Network Accelerators

Jeff (Jun) Zhang, Zahra Ghodsi, Kartheek Rangineni,
Siddharth Garg

New York University

10:00 AM

10:30 AM

 

Break

10:30 AM

11:10 AM

 

Invited Talk: Using Bitwise Machine Learning Models for Resource-Constrained Edge Devices

Dr. Minje Kim

Assistant Professor
Department of Intelligent Systems Engg,
School of Informatics and Computing
Indiana University

11:10 AM

11:35 AM

 

WRPN: Training and Inference using Wide Reduced-Precision Networks

Asit Mishra, Jeffrey J Cook, Eriko Nurvitadhi, Debbie Marr

Accelerator Architecture Lab, Intel Labs

11:35 AM

12:00 PM

 

Time Based Computing (TBC) for Low Power Machine Learning Applications

Somnath Paul, Charles Augustine, and Muhammad M Khellah

Circuit Research Lab,
Intel Corporation

 

Overview:

With singularity in the horizon, machine intelligence is racing to outdo human intelligence in many application areas. Hardware and software architects are hard-pressed to search for unconventional functional capabilities commanded by these requirements. Traditional architectures are being proven to be insufficient in many layers of this capability stack. At this critical juncture in the computing and human history, Soft Computing is evolving as a key technology enabler across the stack. On one hand it allows machines to operate with abstract information and build novel functional faculties needed for human-like problem solving capabilities, while on the other hand it helps bridge the performance and power density gap by allowing hardware architectures to operate in imprecise and probabilistic levels.

 

As an emerging research field, "Computational Intelligence & Soft Computing" poses many challenges: (a) Provide human-like perception and problem solving functionality (b) Build the needed performance/power density with imprecise hardware architectures (c) Develop resilient algorithms capable of operating with noisy information and low precisions (d) provide an execution environment with proper orchestration, compiler/runtime capabilities to identify varying degrees of error tolerance of the application and optimally map them to proper hardware blocks and operating points to bound the error across stack and provide the required precision and capabilities (e) provide end-to-end system designs that combine soft computing platforms with optimal content compression and transmission over noisy stochastic channels to maximize intelligent application performance under latency and power constraints.

 

We hope to encourage discussions on these topics during the workshop via invited talks and selected papers from soliciting submissions from academia and industry.

 

Below is the proposed list of topics for the workshop.  Topics include, but are not restricted to, the following:

 

       Human-like Intelligent applications

o   Autonomous Systems/Robotics

o   Autonomous Driving/Drones

o   Virtual Assistants

o   Augmented Reality/Virtual Reality

o   Natural Language Processing

o   Visual Understanding

     Algorithms

o   Approximate/probabilistic computing

o   Neural Networks/Deep Learning

o   Knowledge Representation & Reasoning

o   Self-Learning/Reinforcement learning 

o   Machine Learning/BigData Analytics

     Execution Environments

o   Compiler/Runtime for hybrid/varying precision

o   Domain-Specific Languages

o   Orchestration/Scheduling

     Hardware Architectures

o   Non Von-Neumann Architectures

o   Near Threshold Voltage Circuits

o   Non-CMOS circuits

o   Hybrid (Analog/Digital) computing

     Content compression and transmission

o   Adaptive application based sensing

o   Encoding and compression for soft computing

o   Varying precision transmission systems

 

In addition to these areas, we also encourage papers on other important topics such as scaling up and out, cluster/datacenter infrastructures, systems software issues and design methodology challenges.

 

Submission Guidelines:

Interested authors are encouraged to submit extended abstracts (1 - 2 pages) or short papers (6 pages) by email to the organizing chairs. The deadline for submission is July 14, 2017. Final (short) papers will be due on August 18, 2017.

 

Important Dates:

Abstract/Paper submission:     August   7, 2017 (extended)

Author Notification:                August 14, 2017

Final Paper Submission:    September   1, 2017

Workshop:                          September 10, 2017