PACT 2017

International Conference on Parallel Architecture and Compilation Techniques
PACT-2017
Portland, Oregon, USA
Sep 9-13, 2017


Dates & Deadlines:

  • March 14, 2017: Paper Deadline
  • May 3-6, 2017: Author Response Period
  • May 24, 2017: Author Notification
  • July 19, 2017: Camera Ready Final Papers
  • September 9-13, 2017: PACT 2017


PACT 2017 Information:

Call for Contributions

Program

Registration

Location


PACT 2017 Organization:


Previous PACTs:
PACT16 PACT15 PACT14 PACT13 PACT12 PACT11 PACT10 PACT09 PACT08 PACT07 PACT06 PACT05 PACT04 PACT03 PACT02 PACT01 PACT00 PACT99

Technical Sponsors




Address questions to: mi.sun.park [at] intel.com

The 26th International Conference on
Parallel Architectures and Compilation Techniques (PACT)
Portland, Oregon, USA
September 9-13, 2017

Main Conference

Day 1 - September 11th, Monday
7:00-8:00 Registration & Breakfast
8:00-8:30 Opening
8:30-9:30 Keynote
Marc Tremblay, Microsoft: “Cloud Performance – AI and Others”
Chair: Ravi Iyer (Intel)
9:30-10:00 Break
10:00-11:40 Session 1: Algorithms and data structures
Chair: Xipeng Shen (North Carolina State)
  • RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees
    Dimitrios Siakavaras, Konstantinos Nikas, Georgios Goumas, and Nectarios Koziris (National Technical University of Athens)
  • Redesigning Go's Built-In Map to Support Concurrent Operations
    Louis Jenkins (Bloomsburg University), Tingzhe Zhou (Lehigh University), and Michael Spear (Lehigh University)
  • MultiGraph: Efficient Graph Processing on GPUs
    Changwan Hong, Aravind Sukumaran-Rajam, Jinsung Kim, P. Sadayappan (The Ohio State University)
  • An Ultra Low-power Hardware Accelerator for Acoustic Scoring in Speech Recognition
    Hamid Tabani, Jose Maria Arnau, Jordi Tubella, and Antonio Gonzalez (Universitat Politècnica de Catalunya)
11:40-1:10 Lunch
1:10-2:50 Session 2: Approximate and speculative computations
Chair: Jaejin Lee (Seoul National University)
  • DrMP: Mixed Precision-aware DRAM for High Performance Approximate and Precise Computing
    Xianwei Zhang, Youtao Zhang, Bruce R. Childers, and Jun Yang (University of Pittsburgh)
  • SAM: Optimizing Multithreaded Cores for Speculative Parallelism
    Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey (MIT), Joel Emer (MIT/Nvidia), and Daniel Sanchez (MIT)
  • Performance Improvement via Always-Abort HTM
    Joseph Izraelevitz (University of Rochester), Lingxiang Xiang (Intel Corporation), and Michael L. Scott (University of Rochester)
  • DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-ahead Architecture
    Raj Parihar (Cadence Design Systems), and Michael C. Huang (University of Rochester)
2:50-3:20 Break
3:20-4:10 Session 3: Data & Emerging Use Cases
Chair: Omesh Tickoo (Intel)
  • Proxy Benchmarks for Emerging Big-data Workloads
    Reena Panda, and Lizy Kurian John (University of Texas at Austin)
  • Lightweight Provenance Service for High Performance Computing
    Dong Dai, Yong Chen (Texas Tech University), Philip Carns, John Jenkins, and Robert Ross (Argonne National Laboratory)
4:10-5:00 Poster presentations
Chair: David Padua (Illinois)
6:00-8:00 Reception + Poster Session (PACT Posters & ACM SRC Posters)
Day 2 - September 12th, Tuesday
7:30-8:30 Registration & Breakfast
8:30-9:30 Keynote
P. Sadayappan, Ohio State University: “Can compilers help us achieve high performance, productivity, and portability?”
Chair: David Padua (Illinois)
9:30-10:00 Break
10:00-11:40 Session 4: Memory 1
Chair: Lawrence Rauchwerger (Texas A&M)
  • Nexus: A New Approach to Replication in Distributed Shared Caches
    Po-An Tsai (MIT), Nathan Beckmann (CMU), and Daniel Sanchez (MIT)
  • Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches
    Priyank Faldu, and Boris Grot (University of Edinburgh)
  • Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology
    Vicent Selfa, Julio Sahuquillo (Universitat Politècnica de València), Lieven Eeckhout (UGENT), Salvador Petit, and Maria E. Gómez (Universitat Politècnica de València)
  • Transparent Dual Memory Compression Architecture
    Seikwon Kim, Seonyoung Lee, Taehoon Kim, and Jaehyuk Huh (KAIST)
11:40-1:10 Lunch
1:10-2:50 Session 5: Best Papers (GPU computing and energy efficiency)
Chair: Kemal Ebcioğlu (Global Supercomputing)
  • End-to-end Deep Learning of Optimization Heuristics
    Chris Cummins, Pavlos Petoumenos (University of Edinburgh), Zheng Wang (Lancaster University), and Hugh Leather (University of Edinburgh)
  • Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU
    Wei Han, Daniel Mawhirter, Bo Wu (Colorado School of Mines), and Matthew Buland (Salesforce)
  • A GPU-Friendly Skiplist Algorithm
    Nurit Moscovici (Technion), Nachshon Cohen (EPFL), and Erez Petrank (Technion)
  • Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency
    Raghavendra Pradyumna Pothukuchi (UIUC), Amin Ansari (Qualcomm), Bhargava Gopireddy, and Josep Torrellas (UIUC)
2:50-3:20 Break
3:20-5:00 Session 6: Memory 2
Chair: Nilesh Jain (Intel)
  • Avoiding TLB Shootdowns through Self-invalidating TLB Entries
    Amro Awad (Sandia National Laboratories), Arkaprava Basu (AMD Research), Sergey Blagodurov (AMD Research), Yan Solihin (North Carolina State University), and Gabriel H. Loh (AMD Research)
  • Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
    Sizhuo Zhang (MIT), Muralidaran Vijayaraghavan (MIT), and Arvind (MIT)
  • Near-Memory Address Translation
    Javier Picorel (EPFL), Djordje Jevdjic (University of Washington), and Babak Falsafi (EPFL)
  • Efficient Checkpointing of Loop-Based Codes for Non-Volatile Main Memory
    Hussein Elnawawy, Mohammad Alshboul, James Tuck, and Yan Solihin (North Carolina State University)
5:35 Bus departs from hotel to excursion (cruise)
Day 3 - September 13th, Wednesday
7:30-8:30 Breakfast & Registration
8:30-9:30 Keynote
Pradeep Dubey, Intel Labs: “AI and The Virtuous Cycle of Compute”
Chair: Srinivas Aluru (Georgia Tech)
9:30-10:00 Break
10:00-10:50 ACM SRC Presentations
Chair: Vijay Janapa Reddi (UT Austin)
11:05-12:20 Session 7: Translation
Chair: Francois Irigoin (MINES Paris Tech)
  • SuperGraph-SLP Auto-Vectorization
    Vasileios Porpodas (Intel Corporation)
  • Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation
    Yu-Ping Liu (National Taiwan University), Ding-Yong Hong, Jan-Jan Wu (Academia Sinica), Sheng-Yu Fu, and Wei-Chung Hsu (National Taiwan University)
  • A Generalized Framework for Automatic Scripting Language Parallelization
    Taewook Oh, Stephen R. Beard, Nick P. Johnson, Sergiy Popovych, and David I. August (Princeton University)
12:20-12:35 Best paper & ACM SRC Awards
Chair: David Padua (Illinois) and Vijay Janapa Reddi (UT Austin)
Conference Close