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Time - Monday, July 10, 2017, 4:00 pm
Location - 302 HRBB

Towards Production-Run Heisenbugs Reproduction on Commercial Hardware

Shiyou Huang
Parasol Laboratory, Department of Computer Science
Texas A&M University

Abstract

We present a new technique, H3, for reproducing Heisenbugs in production runs on commercial hardware. H3 integrates the hardware control flow tracing capability provided in recent Intel processors with symbolic constraint analysis. Compared to a state-of-the-art solution, CLAP, this integration allows H3 to reproduce failures with much lower runtime overhead and much more compact trace. Moreover, it allows us to develop a highly effective core-based constraint reduction technique that significantly reduces the complexity of the generated symbolic constraints. H3 has been implemented for C/C++ and evaluated on both popular bench- marks and real-world applications. It reproduces real- world Heisenbugs with overhead ranging between 1.4%- 23.4%, up to 8X more efficient than CLAP, and incurs only 4.9% runtime overhead on PARSEC benchmarks.

Biography

Shiyou Huang is a Ph.D. candidate supervised by Dr. Jeff Huang in the ASER group of Parasol Lab, Texas A&M University. His research interests include program verification, debugging, symbolic execution, model checking and static analysis. He has already published several papers at top conferences, e.g., OOPSLA, USENIX ATC and ECOOP. He received his B.S. in Computer Science from Huazhong University of Science and Technology in May 2015.